Frequency synthesizing system

ABSTRACT

A frequency synthesizing system includes frequency synthesizing means operative to produce an adjustable intermediate frequency, frequency dividing means for dividing the intermediate frequency by an adjustable division factor to produce an output frequency, setting means operable to set up the desired value of the output frequency, and control means automatically responsive to the setting means to adjust the synthesizing means and the dividing means in dependence on the desired value of the output frequency, such that the value of the intermediate frequency produced by the synthesizing means produces, when divided by the division factor of the dividing means, the desired output frequency.

United states Patent Thrower [451 Nov. 7, 1972 [541 FREQUENCYSYNTHESIZINC SYSTEM [72] Inventor: Keith R. Thrower, Bracknell, En-

gland [73] Assignee: Racal Instruments Limited, Windsor, Berkshire,England [22] Filed: Sept. 30,1971

[211 App]. No.: 185,261

301 Foreign Application Priority om [58] Field of Search ..328/l4, I59,45, 48', 33l/5l 5/1970 Breetz ..328/l4X 2/l97l Noyes ..328/14 PrimaryExaminer-John S. Heyman Attorney'Mason,Mason & Albright [57] ABSTRACT Afrequency synthesizing system includes frequency synthesizing meansoperative to produce an adjustable intermediate frequency, frequencydividing means for dividing the intermediate frequency by an adjustabledivision factor to produce an output frequency, setting means operableto set up the desired value of the output frequency, and control meansautomatically responsive to the setting means to adjust the synthesizingmeans and the dividing means in dependence on the desired value of theoutput. frequency, such that the value of the intermediate frequencyproduced by the synthesizing means produces, when divided by the [56]Rekrences Cited division factor of the dividing means, the desired out-UNITED STATES PATENTS P q y- 3,293,561 12/ 1966 I-Iegarty ..328/ I4 X 10Claims, 5 Drawing Figures 4 e i3 46 20,, lumen 22 SYNTHESIZER +70SYNTHESIZER SlNTHES/ZER -5- F3 F3 3: l Fl 7 Fb l m2 n1 2 MULT/PLIERIIlD/CES PAIENT EDMM 7:912

SHEET 2 OF 5 mm mm The invention relates to frequency synthesizers.

According to the invention, there is provided a frequency synthesizingsystem, including frequency synthesizing means operative to produce anadjustable intermediate frequency, frequency dividing means connected todivide the intermediate frequency by an adjustable division factor toproduce an output frequency, setting means operable to set up thedesired value of the output frequency, and control means automaticallyresponsive to the setting means to adjust the synthesizing means and thedividing means such that the value of intermediate frequency produced bythe synthesizing means produces, when divided by the division factor ofthe dividing means, the desired output frequency.

According to the invention, there is also provided a method of frequencysynthesis, in which an intermediate frequency is synthesized and thendivided to produce the desired output frequency, the division factorbeing automatically selected according to a predetermined programrelating values of division-factors to values of the desired outputfrequency, and the intermediate frequency being automatically selectedaccording to the product of the division factor and the third outputfrequency, such that the intennediate frequency, when divided by thedivision factor, gives the desired output frequency.

A frequency synthesizing system embodying the inparticular totaldivision factor Q for the divider 20). In addition, the control unit 24(in combination with the indices selector 26) sets up a multiplier unit28. The multiplierunit 28 is connected to control the synthes-' izerblocks to 16 such that the value of the frequency F1 on line 18 is, whendivided by the division factor Q or the divider 20, equal to the desiredvalue of the vention, and a method of frequency synthesis according tothe invention, will now be described, by way of example only, and withreference to the accompanying drawings in which:

FIG. 1 is a block circuit diagram of the system;

FIGS. 2, 3 and 4 are more detailed block circuit diagrams of variousparts of the system of FIG. 1; and

FIG. 5 shows waveforms occurring in the system.

In broad outline, the synthesizer system comprises frequencysynthesizing blocks l0, 12, 14 and 16 which are settable by an operatorin a manner to be described to produce an output frequency F l on a line18. The frequency F1 is fed through an automatically variable frequencydivider 20 to produce the required synthesized frequency F0 on an outputline 22. The divider 20 comprises, in this example, two frequencydividing chains in series, the first dividing chain dividing by 10'' andthe second frequency dividing chain dividing by 2", where m can be 0, lor 2, and n can be 0,1, 2 or 3. The total division factor of the divider10 is therefore Q =1 O"'-2". The synthesizer system has a control panel24 with, in this example, five manually operable controls 24A to 24Ewhich are used by the operator to set up the required decade digits ofthe frequency F0 to be synthesized. In the particular example of thesynthesizer to be described, the frequency range covered is 0 to 160 MHz(actually 0.1 to 159.99 MHz). The controls 24A to 24D each have 10settings, Q"to.9, and respectively set up the number of tens of KHz inthe required output frequency, the number of hundreds of KI-Iz, thenumber of units of MHz, and the number of tens of MHz. The control 24Esets the number of hundreds of MHz in the required output frequency, andthus has two settings of l and 0. The control panel 24 controls anindices selector 26 which, for each desired frequency value set up onthe control panel 24,

selects particular values of m and n (that is, it selects a outputfrequency F0.

The synthesizer system will now be described in more specific detail.

In a manner to be explained, the synthesizer blocks 10, 12 and 14 can beset so that the frequency F1 on line l8 is variable between and MHz(actually 80 and 159.99 MHz), that is, variable over one octave. Fl cantherefore be represented by F1=80+1OA+B+CI10+DI100 (in MHz) (1) As Q thetotal division factor of the divider 20, then Fo=Fl/Q. (2) Q is variablefrom 1 (when m and n are both zero) and 800 (when m is 2 and n is 3),thus making F0 variable between 0.1 MHz and 159.99 MHz.

The synthesizer block 10 synthesizes the digit D (see equation 1). It isconnectedto receive a fixed frequen cy Fr on a line 40 which, in thisexample, is 0.6 MHz,

and a variable frequency, F on a line 42. The line 42 i is connected toa switch 44 which has 10 settings, numbered 0, 1, 2, .j. 9. The 10 inputterminals of the switch 44 are respectively connected to receive inputsof different frequency. Thus, when the switch is in setting 0, an inputfrequency of 5.4 MHz is connected to line 42, and the input frequencyincreases by 0.1 MHz per switch setting, up to 6.3 for setting 9. Theillustration of switch 44 is purely diagrammatic, and in a practicalcase the switch would be electronic in nature. As shown, it iscontrolled by a logic unit 46 which is connected by a channel 48 to themultiplier unit 28. The channel 48 has four lines which carry, in binarycoded decimal (BCD) form, signals representing that setting of switch 44which, as determined by the multiplier 28, is required in order toproduce the correct value of thedigit D in the frequency F1 on line 18.If the multiplier 28 determines that the required value of D is 2, say,then it produces, in BCD form, a signal representing decimal 2 onchannel 48 and switch 44 is set into setting 2 by the-logic unit 46 thusgiving F a value of 5.6 MHz; and similarly for the other values of D. Itwill be seen that the different possible values of F (5.4 to 6.3 MHz)are such that F2=Fr+F =0.6+F From equation (3) above, it thereforefollows that F2 6 D/ l 0 (5) The output frequency F2 is divided by 10 ina fixed divider 50 which therefore produces an output frequency of F3where The frequency F3 is one input to the synthesizer block 12 which issimilar in construction operation to the synthesizer block 10, andreceives a second input, F on a line 52. It produces an output F4 on aline 53 where i The logic unit 74 differs from the other logic units 46,56 and 68in that the switch setting which it t produces is notnumerically equal to the decimal value determined by the multiplier 28.Thus, for example, if

the multiplier 28 determines that the desired value of the digit C is 6,then it produces, in BCD form, a signal on channel 58 representingdecimal 6 and the logic unit 56 is caused to set the switch 54 intosetting .6, thus givingF a value of 6 .0 MHz; and correspondingly forthe othervalues of.

It will be seen that the different possible values o fF (5.4 to 6.3 MHz)are such that F =5.4+C/10 From equations (6), (7) and (8), it followsthat The synthesizer block 14 is similar in construction and operationto the synthesizer block 10 and 12. It

receives an input frequency F A on a line 60 and second input frequencyF on an input line 62, and produces an output frequency F on a line 64where F5 FA F5 The frequency F B is controlled by a switch 66 which hassettings, 0,' l, 2, 9. The IO'inputs of the switch 66 are respectivelyconnected to receive fixed frequencies of 4, 5, 6, Q 188 13 MHz. Switch66 (which, like the switches 44 and 54, is shown only diagrammatically)is controlled by a logic unit 68 which is connected by a channel 70 tothe multiplier 28. Channel 70 has four lines which carry, in BCD form,the required value of the digit B as determined by the multiplier 28. Ifthe multiplier 28 determines that the required value of B is 6, then asignal representing decimal 6 is produced in BCD form on channel 70 andthe logic unit 68 is caused to set switch 66 into setting 6 to give F Ba value of 10 MHz; and correspondingly for the other values of B.Therefore F, 4 B 1 1 The frequency F is controlled by a switch 72 whichhas eight settings, 0, l, 2, 7. The eight inputs of the switch 72' arerespectively connected to receive frequencies of 70, 80, 140 MHz. Switch72 (which, like the other switches, is shown only diagrammatically) iscontrolled by a logic unit 74 which is connected by a channel 76 to themultiplier 28. The logic unit 74 responds to the signal received onchannel 76 by producing an output indicating the desired value of thedigit A and setting the switch 72 accordingly. Thus if ;the-desired-value of A is 6, then the switch. 72 is set intosetting6 and soon.it will be seen that the range of possible values for F A is such thatof the signal received via channel 76. The reason for this is explainedlater. Table I below indicates the switch setting produced by the logicunit 74 for each signal value on channel 76.

TABLE 1 Required value Decimal value Output of Logic Unit of Digit A ofsignal in 74 and corresponding channel 76 setting of switch 72 0 8 o l 9l 2 0 2 3 l 3 From equations 10 11' and 12 it will be seen that Thesynthesizer block 16 receives the two frequencies F4 and F5 and, beingsimilar in construction and operation to the other synthesizer blocks,produces the output frequency Fl where F1=F5 +F6 From equations (9),(l3) and 14), it will be seen that as required.

As explained, the indices selector 26 is connected to the control panel24 by five channels 90, 92, 94, 96, 98.

Each of channels to 96 has four lines which carry, in BCD form, signalsrepresenting the setting of the controls 24A to 24D. Channel 98 has onlyone line which carries a binary 0 or a binary 1 dependent on whethercontrol 24E is set to 0 or 1. The indices selec-' tor 26 has an outputchannel 100 having seven lines which can respectively carry the binarysignals m0, m1, m2, n0, n1, n2, n3. The selector 26 responds to thesignals received on the channels 92 to 98 by determining the requiredvalue of Q, the division factor of divider 2O (Q= 10" 2") and determinesthe coding of the seven lines of channel 100 accordingly. Thus, forexample, if the selector 26 determines that the required value of 'Q is8, then the required values of m and n are 0 and 3, and it sets lines mand n to binary l and the remaining five lines in channel 100 to binary0, and similarly for the other values of m and n. I

Table H below shows the values of Q and F0 (in MHz) for different valuesof m and n, having regard to the fact that F1 is variable between 80 and(actually 159.99) MHz.

The serial BCD multiplier unit 136 (see FIG. 4) comprises four AND gates148 to 151,'all of which are connected to receive the clock signals onthe line 134 and which have their second inputs respectively connectedto receive the signals P2 to P5. The outputs of the AND gates 148 to 151are respectively connected to the inputs of scale of ten cascadeddecimal counters 153 to 156. The outputs of the counters arerespectively connected to BCD encoders 158 to 164. The latterrespectively feed the channels 48, 58, 70 and 76.

Each signal P2 opens the gate 148. Clock pulses from line 134 thereforepass through the gate 148, and are counted up by the counter 153. Thenumber of clock pulses passing into the counter during each pulse of thesignal P2 is proportional to the length of that pulse, and thus directlyproportional to the BCD value presented on channel 90. In other words,the number of pulses counted by counter 153 during each pulse of signalP2 is equal to the product of the decimal value set up by the control24A and the division factor, Q, selected by the indices selector 26.

A pulse of signal P3 now arrives and opens gate 149. The number of clockpulses on line 134 which are counted by the counter 154 is thereforeequal to the product of the setting of control 24B and the divisionfactor Q. In similar fashion, pulses P4 and P5 open gates 150 and 151and cause the counters 155 and 156 to count the products of Q and thesettings of the controls 24C and 24D. Since the counters are cascaded,their outputs continuously carry, in decimal form, the last four digitsof the product of Q and the number set up by the controls 24A to 24D.The BCD encoders 158 to 164 convert the decimal signals into BCD formand respectively energize the channels 48, 58, 70 and 76. The countersare reset during each pulse 411 by means of a line 165, while theencoders are updated during each pulse (#1 (but before the counters arereset) by means of a line 166.

It will be observed that the product produced by the multiplier 28 isnot directly affected by the setting of the control 24E. However, theproduct produced is indirectly affected by the setting of the control24E since the latter affects the value of the division factor Q which inturn affects the value of the product produced by the multiplier 28.

It will also be noted that the output of the multiplier 28 does notindicate the value of the most significant digit of the required valueof F1. However, since F1 cannot be more than 159.99 MHz, this digit canonly be decimal l or 0. Furthermore, F 1 cannot be less than 80 MHz.Therefore, when the decimal value of the digit presented on channel 76is 8 or 9, the most significant digit of F 1 must be zero, and when thedecimal value of the digit on channel 76 has the value of 0, l, 2, 3, 4or 5 (it cannot have the value of 6 or 7), the most significant digit ofF 1 must be 1. Thus, the output from the multiplier 28 implicitlyindicates the value of the most significant digit of F l The decimalvalue of the output on channel 76 represents, therefore, the number oftens of MHZ in the required value of F 1. This number must lie withinthe range 8 to (since the minimum value of F1 is 80 MHz and the maximumis 159.99 MHz). If the required number of tens of MHz is 8 or 9, this isindicated directly by the decimal value of the output in channel 76;ifthe number oftensis 10, 1 1, l2, 13, 14 or 15, this is indicated inchannel 76 by the number 0, 1, 2, 3, 4 or 5, respectively. Since thesynthesizing system inherently provides a value for F 1 of 80 MHz, itfollows that the value of A (see equation 1) must be 8 less than thenumber of tens indicated by the decimal value of the output on channel76. This is taken care of by the logic unit 74 in the manner explainedabove with reference to Table I.

The operation of the complete synthesizer will now be considered using aspecific numerical example.

Let it be assumed that the required output frequency, F0 is 29.43. Thus,the controls 24A to 24E would respectively be set to decimal values of3, 4, 9, 2 and 0 and BCD coded versions of these decimal values would bepresented to the indices selector 26 on the channels to 98. In addition,the BCD values of the settings of controls 24A to 24D would be presentedon channels 90 to 96 to the multiplier 28.

In the manner explained above, and as shown by Tables H and III, theindices selector 26 would determine that the required value for m is 0and for n is 2, that is, Q 4. Therefore, the indices selector 26 wouldproduce a binary l on the lines m0 and n2 in the channel 100, thusenabling the AND gates 102 and 124 (FIG. 2) of the divider 20, the otherlines of the channel being maintained at binary 0.

In the manner explained, the multiplier unit 28 multiplies the decimalvalue of the total signal presented to it on channels 90 to 96 by thedivision factor Q. The resultant product is 117.72, of which, asexplained above, only the last four digits appear on the output channels48, 58, 70 and 76. Thus, channel 48 carries decimal 2, channel 58carries decimal 7, channel 70 carries decimal 7, and channel 76 carriesdecimal 1, these numbers of course being presented in BCD form.

Therefore, the logic unit 46 sets the switch 44 (FIG. 1) into setting 2,thus giving frequency F D a value of 5.6MH2. Therefore, from equations(4) and (5), F2 is 6.2MHz, and F3 is 0.62MHz.

Similarly, logic unit 56 sets the switch 54 into setting 7, thus givingF a value of 6.1MHz. Therefore, from equation (7), F4 becomes 6.72 MHz.

The logic unit 68 determines that the required value of B is 7, and setsthe switch 66 into the setting 7, thus giving the signal F a value of llMHz. The logic unit 74 determines from the signal on channel 76(decimal 1)- that the required value of A is 3 (see Table l) and setsthe switch 72 into the setting 3, thus giving the signal F A a value of100MHz. Therefore, from equation (10) it follows that the synthesizerblock 14 produces an output frequency, F5, of l 1 lMHz.

From equation (14), it follows that the output frequency F 1 produced online 18 is given by Fl=6.72+ 111 MHz =ll7.72Ml-Iz Therefore, the outputfrequency F0 produced on line 22 is given by Fo/Q= 117.72/4= 29.43, asrequired.

From the above, it will be seen that the synthesizer system describedenables the synthesis of output frequencies in a large frequency range(0 to MHz, more than 1 octave), and yet avoids the use of very highfrequencies with the attendant difficulties of The values marked shouldtheoretically be 15.99 I

and 1.59 but the system is arranged to limit these values to the figuresgiven so as to avoid overlap between the range of outputs obtainablewhen m and n 3 and v the range obtainable when m 1 and n 0, and to avoidoverlap between the range obtainable when m l and n 3 and the rangeobtainable when m 2 and n 0.

If the decimal values of the digits of F0 respectively set up by thecontrols 24E to 24A are given by K K K K K respectively, then Table IIIbelow shows the logic required to produce the signals m0, ml, m2, n0,n1, n2, n3. In column 3 of the Table, the decimal numbers in bracketsindicate the decimal values of the digits K, to K In a manner which willbe clear to those skilled in the art, the indices selector 26 containslogic required to satisfy Table III and to produce the required valuesof signals m0 to n3 for each required value of F0.

. TABLE III Function to be Truth Statement Gating Function Realized forthe Function m0 lfK,islorK,isl-9 K,(1)+K,(l-9) (i.e. 10-15999 MHz) If K,is 0, and K, is 0, and K,(0).K,(O).K, (l-9 m1 K is l-9 (i.e. 1-9.99 MHz)If K, is 0, and K, is 0, and K,(O).K. (O).K 0).K.(AU-9) m2 K is O, and Kis l-9 (i.e. (Altirinatively r710,

- m 0.1-0.99 MHz) 7 If m0, and K is l; or ifm0, mtg K K, (8-9) and K is8-9; or n0 lfm1,andK,is l;orifm0, m1' [K,(l)+K (8-9) and K is 8-9; orlfm2,ar|dK,isl;orifm0, m2[K,,(l)+K,

and K, is 8-9 If m0, and K is 4-7; or m 1 n1 Ifm1,andl( is4-7;orm1[K,(4-7)]+ lfm2,andK,is4-7 m2 [K (4-7)] If m0, and K, is 2-3; or m0[K,(2-3)]+ n2 If ml, and K is 2-3; or ml [K (23)]-l If m2, and K, is 2-3 m2[K (2-3)] lfm0,andK isl;or m0{l(,(l)]+ n3 lfml andK is 1;0r m1[K,- (l)]+lfm2,andl( is1 m2[K.(l)]

(Alternatively, R0711 FIG. 2 illustrates the divider 20. It comprisesthree two-input AND gates 102, 104, and 106 which are respectivelyconnected to be enabled by the signals m0, ml, and m2. Gate 102 has itssecond input connected directly to line 18 (FIG. 1). Gate 104 has itssecond input connected to line 18 through a frequency divider 108 havinga fixed division factor of 10, while the second input of gate 106 isconnected to line 18 through frequency divider 108 and a secondfrequency divider 1 10 which also has a fixed division factor of 10. Theoutputs of the gates 102 to 106 are connected through an OR gate 112 toa chain of three binary dividers or flip-flops 114, 116, 118. The outputof the OR gate 112 is connected to one input of a two-input AND gate120, whilethe outputs of the flip-flops 114 to 118' are respectivelyconnected to one input of further two-input AND gates 122, 124, 126. Thesecond input of each of the AND gates 120 to 126 is respectivelyconnected to receive the signals n0, n1, n2, n3. The outputs of the ANDgates 120 to 126 are connected to the line 22 (FIG. 1) throughan OR gate128.

FIG. 2 makes clear how the total division factor Q applied between lines18 and 22 is determined by the values of the signals m0 to n3.

As indicated above, the multiplier 28 determines the value required forthe frequency F1 in order to produce the correct value for F0 havingregard to the selected division factor, Q, and will now be described indetail.

As shown in FIG. 3, the multiplier 28 comprises a synchronous clockdivider 126 which is connected to line 128 which comprises pulses at afixed repetition frequency of 10/800 MHz, each pulse thus defining aperiod, T, of so s; these pulses are applied as one input to afive-phase clock generator 130 and also to a pulse generator 132. Thedivider 126 has a second output, on a line 134, comprising pulses at a.frequency of 10Q/800 MHz, where Q is determined by the values of thesignals presented on the channel 100: line 134 feeds a serial dynamicBCD multiplier unit136.

The five-phase clock generator 130 has five output lines whichrespectively carry signals 411 to 5. The waveforms of the outputs 4:1 tos are shown in FIG. 5. Each output comprises a succession of negative800 1.8 pulses but the outputs are phase displaced with respect to eachother.

The pulse generator 132 is controlled by the binary coded decimalsignals received from the control panel 24 by means of the channels 90to 96 and has four output lines 138, 140, 142, and 144 carrying signalsP2, P3, P4 and P5 respectively. A signal P2 is produced on line 138under control of theBCD-sigrral received on channel 90. Thus, as shownin FIG. 5, the signal P2 comprises a series of positive pulses whosetrailing edges are in phase with the pulses of the signal (#2 but thelength of each pulse of the signal P2, in multiples of ;:8, is directlyproportional to the value of the BCD signal on the channel 90. Thus, ifthe BCD value presented on channel is decimal 1, then each pulse of thesignal P2 will have a length of 80p.S (that is, 1 times 80,48); If theBCD signal on channel 90 is decimal 6, for example, then each pulse ofthe signal P2 will have a length of 480p.S (that is, 6 times 80p.S orsix-tenths of the length of each pulse of the signal (1)2); and so on.In similar fashion, the signals P3 to P5 are controlled by the BCDsignals presented on channels 92 to 96 respectively and, as shown inFIG. 5, the signals P3 to P5 respectively comprise trains of pulseswhose trailing edges are in phase with the signals 3 to screening andrelatively high noise values. The synthesizer described and illustrateduses comparatively low frequencies which do not impose unusuallydifficult screening requirements or produce unacceptable noise levels(in fact, the divider 20 has the effect of reducing the noise when thedivision factor Q is relatively high). The synthesizer described andillustrated overcomes these disadvantages by virtue of its use of thedivider 20. The provision of the indices selector 26 and the multiplier28 ensures that the divider 20 does not render the synthesizer difficultto set up: if, for example, the indices selector 26 and the multiplier28 were not present, and the divider 20 were made manually settable,then it would be necessary for the operator first to calculate orotherwise ascertain the correct division factor required for his desiredoutput frequency, then to calculate the corresponding value of F1, andfinally to set up the desired values of Q and Fl. This would be a timeconsuming process, and would also suffer from the disadvantage that thevalue of the output frequency F would not be immediately apparent fromthe setting of the controls of the synthesizer. These disadvantages areovercome by the provision of the indices selector 26 and the multiplier28.

Each synthesizer block 10 to 16 may, for example, comprise a simplemixer with filtering means to select the upper sideband as the requiredoutput frequency. Instead, however, each synthesizer block may comprisea mixer which mixes one of the inputfrequencies with the output of avoltage controlled oscillator, and a phase sensitive detector connectedto compare the lower sideband output from the mixer with the other ofthe two input frequencies, the phase sensitive detector being connectedto control the voltage controlled oscillator in a sense such as to tendto maintain the difference between the two frequencies compared at zero.

Although the divider 20 has been indicated as dividing by a factor givenby 10'". 2" where m and n are variable, the divider may divide by anyother suitable variable factor of different mathematical'form.

In a modification, the system is fitted with a range switch whichenables different possible frequency ranges for the output frequency F0to be selected: for example, for range setting l,Fo. would be variablebetween 10 and 159.99, for range setting 2,F0 would be variable between1 and 15.999, and for range setting 3,F0 would be variable between 0.1and 1.5999. In order to achieve the desired ranges, the selection of thedivide-by-lO dividers in the divider 20 would be controlled by the rangeswitch and would not be controlled by the indices selector 26 whichwould only determine changes in the value of the signal n. Thus in rangesetting 1, the range switch would select neither of the two divide-by-lOdividers 108, 110. In setting 2, the switch would select divider 108alone, while in setting 3 it would select both dividers 108 and 110. Themultiplier 28 would only respond to changes in the signal n and would beunaffected by the range change switch.

This method of range changing is advantageous in that it reduces themultiplication factor to be employed by the multiplier 28 to a maximumof 8. Since the multiplier 28 is dynamic in operation, it takes longerto carry out multiplication at high multiplication factors than at lowfactors, and the range changing method described enables excessivedelays to be avoided.

What I claim is:

1 .1. A frequency synthesizing system, comprising frequency synthesizingmeans operative to produce an adjustable intermediate frequency,frequency dividing means connected to receive the intermediate frequencyand to divide it by an ad- 7 -justable division factor to produce anoutput frequency, setting means operable to set up a desired value ofthe output frequency, and control means connected to the setting meansto respond to the value of the output frequency set up thereby and alsoconnected to the synthesizing means and the dividing means to controlthe values of the said intermediate frequency and of the division factorin dependence on the value of the output frequency set up, such that thevalue of intermediate frequency produces, when divided by the divisionfactor of the dividing means, the desired output frequency. 2. A systemaccording to claim 1, in which the control means comprises selectingmeans operative to produce, for each desired value of the outputfrequency set up by the setting means, a different and predeterminedfirst control output representing a particular value of division factor,multiplying means connected to the setting means and the selecting meansand operative to multiply the desired value of the output frequency setup by the setting means and the first control output to produce a secondcontrol output, means feeding the first control output to the dividingmeans to set the division factor thereof, and

means feeding the second control output to the frequency synthesizingmeans to set the value of the said intermediate frequency.

3. A system according to claim 2, in which the dividwhereby to vary thevalue of the division factor.

4. A system according to claim 3, in which the dividing means comprisesmeans for dividing the intermediate frequency by an additional factor ofY, where Y is a fixed integer and y is an integer which is manuallyvariable to alter the range of the output frequency.

5. A system according to claim 2, in which the dividing means comprisesmeans operative to divide the intermediate frequency by a divisionfactor of X Y", where X and Y are fixed integers, and x and y areintegers which are varied in dependence on the value of the fust controloutput, whereby to vary the value of the division factor.

6. A system according to claim 5, in which X is 2 and Y is 10.

7. A system according to claim 1, in which the frequency synthesizingmeans comprises a plurality of synthesizer arrangements each operativeto synthesize a separate frequency, and

summing means connected to sum the separate frequencies to produce thesaid intermediate frequency,

each synthesizing arrangement comprising means responsive to the controlmeans to set the value of the said separate frequency which itsynthesizes whereby that frequency determines the value of a respectiveone of the decades of the said intermediate frequency.

8. A system according to claim 2, in which the frequency synthesizingmeans comprises a plurality of synthesizer arrangements each operativeto synthesize a respective individually variable frequency which isvariable stepwise from a predetermined datum frequency, and

summing means for summing the individually variable frequencies toproduce the said intermediate frequency,

each synthesizer arrangement comprising means responsive to the saidsecond control output to vary the value of the respective individuallyvariable frequency stepwise in dependence thereon, the

' various datum frequencies and the step sizes in the synthesizerarrangements being selected such that the value of each individuallyvariable frequency determines a different one of the decades of the saidintermediate frequency.

9. A system according to claim 2, in which the frequency synthesizingmeans comprises a plurality of synthesizer arrangements each operativeto synthesize a separate frequency, and

output means connected to add these separate frequencies to produce theintermediate frequency each synthesizer arrangement comprising means foradding two frequencies each having a predetermined datum value and atleast one of which is variable stepwise in predetermined steps from thedatum value, and means responsive to the said second control output tovary the variable frequency, the said datum value and the sizes of thestep variations in the variable frequencies being such that thefrequency synthesized by each synthesizer arrangement determines thevalue of a respective one of the decades of the said intermediatefrequency. 10. A system according to claim 9, in which the intermediatefrequency comprises the sum of a fixed frequency and a variablefrequency, the variable frequency comprising four decades, and in which:

there are three said synthesizing arrangements,

the firstv synthesizer arrangement is connected to add a firstfixedfrequency fixed at .a predetermined predetermined steps'fromapredetermined datum value, and includes means responsive to the saidsecond control output to vary the value of the second variable frequencystepwise whereby to produce a second synthesized frequency,

the third synthesizer arrangement is connected to 7 add third and fourthvariable frequencies variable in redeterrnin ste from resctiveredetermireed datum vfiuesy nd includ s means responsive to thesaid second control output to vary the values of the third and fourthvariable frequencies stepwise whereby to produce a third synthesizedfrequency,

the said output summing means is connected to receive and sum the saidsecond and third synthesized frequencies whereby to produce the saidintermediate frequency, a

the datum values of the first fixed frequency and of the first, second,third and fourth variable frequencies and the sizes of the predeterminedsteps of the latter frequencies are such that the first variablefrequency is variable to vary the value of the least significant decadein the said intermediate frequency, the second variable frequency isvariable to vary the value of the, next more significant decade thereof,and the third and fourth variable frequencies are respectively variableto vary the values of the two most significant decades thereof.

I I I i l Notice of Adverse Decision in Interference In Interference No.98,445, involving Patent No. 3,7 02,441, K. R. Thrower, FREQUENCYSYNTHESIZING SYSTEM, final judgment adverse to the patentee Was renderedJuly 25, 197 7 as to claims 1, 2, 3, 4, 5 and 6.

[Ofiicial Gazette September 20, 1977.]

1. A frequency synthesizing system, comprising frequency synthesizingmeans operative to produce an adjustable intermediate frequency,frequency dividing means connected to receive the intermediate frequencyand to divide it by an adjustable division factor to produce an outputfrequency, setting means operable to set up a desired value of theoutput frequency, and control means connected to the setting means torespond to the value of the output frequency set up thereby and alsoconnected to the synthesizing means and the dividing means to controlthe values of the said intermediate frequency and of the division factorin dependence on the value of the output frequency set up, such that thevalue of intermediate frequency produces, when divided by the divisionfactor of the dividing means, the desired output frequency.
 2. A systemaccording to claim 1, in which the control means comprises selectingmeans operative to produce, for each desired vAlue of the outputfrequency set up by the setting means, a different and predeterminedfirst control output representing a particular value of division factor,multiplying means connected to the setting means and the selecting meansand operative to multiply the desired value of the output frequency setup by the setting means and the first control output to produce a secondcontrol output, means feeding the first control output to the dividingmeans to set the division factor thereof, and means feeding the secondcontrol output to the frequency synthesizing means to set the value ofthe said intermediate frequency.
 3. A system according to claim 2, inwhich the dividing means comprises means operative to divide theintermediate frequency by a division factor of Xx, where X is a fixedinteger and x is an integer which is varied in dependence on the valueof the first control output whereby to vary the value of the divisionfactor.
 4. A system according to claim 3, in which the dividing meanscomprises means for dividing the intermediate frequency by an additionalfactor of Yy, where Y is a fixed integer and y is an integer which ismanually variable to alter the range of the output frequency.
 5. Asystem according to claim 2, in which the dividing means comprises meansoperative to divide the intermediate frequency by a division factor ofXx . Yy, where X and Y are fixed integers, and x and y are integerswhich are varied in dependence on the value of the first control output,whereby to vary the value of the division factor.
 6. A system accordingto claim 5, in which X is 2 and Y is
 10. 7. A system according to claim1, in which the frequency synthesizing means comprises a plurality ofsynthesizer arrangements each operative to synthesize a separatefrequency, and summing means connected to sum the separate frequenciesto produce the said intermediate frequency, each synthesizingarrangement comprising means responsive to the control means to set thevalue of the said separate frequency which it synthesizes whereby thatfrequency determines the value of a respective one of the decades of thesaid intermediate frequency.
 8. A system according to claim 2, in whichthe frequency synthesizing means comprises a plurality of synthesizerarrangements each operative to synthesize a respective individuallyvariable frequency which is variable stepwise from a predetermined datumfrequency, and summing means for summing the individually variablefrequencies to produce the said intermediate frequency, each synthesizerarrangement comprising means responsive to the said second controloutput to vary the value of the respective individually variablefrequency stepwise in dependence thereon, the various datum frequenciesand the step sizes in the synthesizer arrangements being selected suchthat the value of each individually variable frequency determines adifferent one of the decades of the said intermediate frequency.
 9. Asystem according to claim 2, in which the frequency synthesizing meanscomprises a plurality of synthesizer arrangements each operative tosynthesize a separate frequency, and output means connected to add theseseparate frequencies to produce the intermediate frequency, eachsynthesizer arrangement comprising means for adding two frequencies eachhaving a predetermined datum value and at least one of which is variablestepwise in predetermined steps from the datum value, and meansresponsive to the said second control output to vary the variablefrequency, the said datum value and the sizes of the step variations inthe variable frequencies being such that the frequency synthesized byeach synthesizer arrangement determines the value of a respective one ofthe decades of the said intermediate frequency.
 10. A system accordingto claim 9, in which the intermediate frequency comprises the sUm of afixed frequency and a variable frequency, the variable frequencycomprising four decades, and in which: there are three said synthesizingarrangements, the first synthesizer arrangement is connected to add afirst fixed frequency fixed at a predetermined value and a firstvariable frequency variable in predetermined steps from a predetermineddatum value, and includes means responsive to the said second controloutput to vary the value of the first variable frequency stepwisewhereby to produce a first synthesized frequency, the second synthesizerarrangement is connected to add the said first synthesized frequency anda second variable frequency which is variable in predetermined stepsfrom a predetermined datum value, and includes means responsive to thesaid second control output to vary the value of the second variablefrequency stepwise whereby to produce a second synthesized frequency,the third synthesizer arrangement is connected to add third and fourthvariable frequencies variable in predetermined steps from respectivepredetermined datum values, and includes means responsive to the saidsecond control output to vary the values of the third and fourthvariable frequencies stepwise whereby to produce a third synthesizedfrequency, the said output summing means is connected to receive and sumthe said second and third synthesized frequencies whereby to produce thesaid intermediate frequency, the datum values of the first fixedfrequency and of the first, second, third and fourth variablefrequencies and the sizes of the predetermined steps of the latterfrequencies are such that the first variable frequency is variable tovary the value of the least significant decade in the said intermediatefrequency, the second variable frequency is variable to vary the valueof the next more significant decade thereof, and the third and fourthvariable frequencies are respectively variable to vary the values of thetwo most significant decades thereof.